Present flash technologies have encountered significant challenges for scaling such as scaling of program/erase (P/E) voltage, speed, reliability, number of charges stored per floating gate and their variability. Attempts to solve such issues have included employing RRAMs due to their scalability, highly competitive speed, endurance, and retention properties. RRAMs have been placed within contacts, above contacts, between M2 and M3 layers, and above backend layers. Single transistor single resistor (1T1R) RRAMs, which are desirably bipolar and have a high access current, also have a large cell size of 8F2 or higher and are not easily scalable. Single diode single resistor (1D1R) RRAMs, on the other hand, have a smaller cell size of 4F2 or higher, and are easily scalable, but are unipolar and have a low access current. In addition, 1D1R RRAMs employ metal oxide diodes or organic diodes, which are compatible with back-end-of-line (BEOL) processes because of processing temperatures less than 400° C. However, the diodes of such materials are not tunable, have inferior diode performance (i.e., low forward current due to large band-gap), which leads to larger cell area and a high Vdd of 3 to 4.5 V, which is not compatible with low Vdd technology.
A need therefore exists for methodology enabling fabrication of RRAMs which have a small cell size, are easily scalable, have a high access current, and are bipolar, and the resulting product.